1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, relates to semiconductor devices having an even surface of an interlayer insulating film for insulating and isolating an upper layer interconnection and a lower layer interconnection from each other. The present invention further relates to a method of manufacturing such semiconductor devices.
2. Description of the Background Art
FIG. 6 is a cross-sectional view of a semiconductor device having a conventional multilevel interconnection structure. Referring to FIG. 6, an element 20 is formed over a semiconductor substrate 1. An underlying insulating film 2 is formed over semiconductor substrate 1, covering element 20. Underlying insulating film 2 is formed of silicon type insulating film and has its surface made even by reflow (thermal treatment at about 900.degree. C. or above). A gate, which is part of element 20, is formed of polysilicon and has large heat resistance. Therefore, the surface of underlying insulating film 2 can be made even by the reflow. If the interconnection layer is formed of aluminum which has inferior resistance to heat, such reflow treatment can not be employed.
A lower aluminum interconnection 6 (having inferior resistance to heat) is formed on underlying insulating film 2, having a pattern of stepped portions. A lower interlayer insulating film 3 is formed over semiconductor substrate 1, covering aluminum interconnection 6. Lower interlayer insulating film 3 is a silicon oxide film and formed by chemical vapor deposition (hereinafter referred to as CVD). Lower interlayer insulating film 3 is provided for preventing a crack in a spin on glass film (SOG film) to be formed later.
An SOG film 4 is formed on lower interlayer insulating film 3 for making even the surface of lower interlayer insulating film 3. An upper interlayer insulating film 5 is formed on SOG film 4. Upper interlayer insulating film 5 is a silicon oxide film and formed by CVD.
A via hole 23 is made in lower interlayer insulating film 3, SOG film 4 and upper interlayer insulating film 5, for exposing part of the surface of lower aluminum interconnection 6.
An upper aluminum interconnection layer 22 electrically connected to lower aluminum interconnection 6 through via hole 23 is provided on upper interlayer insulating film 5.
In the conventional semiconductor device as stated above, referring to FIG. 6, the surface having the pattern of recessed portions was made even, thereby obtaining an even surface of interlayer insulating film 5 by filling the recessed portions of the pattern with SOG film 4 .
However, referring to FIG. 7, if SOG film 4 is made thick in order to increase the degree of evenness, a crack 4a is caused in SOG film 4. If crack 4a is caused in SOG film 4, a valley 5a is formed on the surface of upper interlayer insulating film 5 to be formed on SOG film 4. An aluminum interconnection layer is formed on upper interlayer insulating film 5 and then the aluminum interconnection layer is patterned under such a condition, so that residue 22a of aluminum is left in valley 5a.
Residue 22a of aluminum was a cause of a short circuit. Also, crack 4a in SOG film 4 caused a problem that the surface of upper interlayer insulating film 5 was not made even.
Accordingly, SOG film 4 could not be formed thick in the conventional semiconductor device. If SOG film 4 can not be formed thick, it causes the following problems.
Referring to FIG. 7, if the distance between aluminum interconnections 6 is long (generally 10 .mu.m above), the surface of interlayer insulating film 5 can not be evened. As a result, working accuracy of upper aluminum interconnection 22 is decreased, causing a short circuit or the like.